Additive White Gaussian Noise (AWGN) and fading are the key factors affecting the quality of wireless communication. Iterative receivers using the concept of feedback remove the effect of AWGN and fading during multiple iterations through the concept of Turbo Decoding, Turbo Demodulation and Turbo Equalization. This project focuses on development of a Turbo Receiver implementing three turbo processes on a single hardware architecture. To address the flexibility related to different wireless standards, the architecture is based on Application Specific Instruction Processor (ASIP) whereas the communication is handled through the use of Network on Chip (NoC). Three different ASIPs have been developed for decoding, demapping and MIMO Equalization. In each ASIP data path is designed in such a way that algorithm level parallelism is implemented to get the best compromise between flexibility and throughput. Data level parallelism is achieved through adding multiple instances of each ASIP which makes the architecture scalable. Additionally, NoC are used which ensure reliable communication between multiple ASIPs.